High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

• Published in: Japanese Journal of Applied Physics 2005-04, Vol.44 (4S), p.2210
• Main Authors: Takahashi, Kensuke, Manabe, Kenzo, Morioka, Ayuka, Ikarashi, Taeko, Yoshihara, Takuya, Watanabe, Heiji, Tatsumi, Toru
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.44.2210

Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of ±0.5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm -2 at a gate bias of Vth+0.6 V.