Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array

A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random acce...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2005-04, Vol.44 (4S), p.2715
Main Authors: Kim, Hyun-Soo, Yamamoto, Shuu'ichirou, Ishikawa, Toru, Fuchikami, Takaaki, Ohki, Hiroshi, Ishiwara, Hiroshi
Format: Article
Language:English
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Summary:A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 10 4 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 10 4 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.44.2715