Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array

A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random acce...

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Published in:Japanese Journal of Applied Physics 2005-04, Vol.44 (4S), p.2715
Main Authors: Kim, Hyun-Soo, Yamamoto, Shuu'ichirou, Ishikawa, Toru, Fuchikami, Takaaki, Ohki, Hiroshi, Ishiwara, Hiroshi
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cited_by cdi_FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33
cites cdi_FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33
container_end_page
container_issue 4S
container_start_page 2715
container_title Japanese Journal of Applied Physics
container_volume 44
creator Kim, Hyun-Soo
Yamamoto, Shuu'ichirou
Ishikawa, Toru
Fuchikami, Takaaki
Ohki, Hiroshi
Ishiwara, Hiroshi
description A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 10 4 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 10 4 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.
doi_str_mv 10.1143/JJAP.44.2715
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fullrecord <record><control><sourceid>crossref</sourceid><recordid>TN_cdi_crossref_primary_10_1143_JJAP_44_2715</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10_1143_JJAP_44_2715</sourcerecordid><originalsourceid>FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33</originalsourceid><addsrcrecordid>eNotkM1OwzAQhC0EEqFw4wH8ALh4_RM3xyiiQFUEh3C2bMcWgbSpNrmEpydROY1mpJnVfoTcA18DKPm425Ufa6XWwoC-IBlIZZjiub4kGecCmCqEuCY3w_A921wryMjn1nlsgxvb_kjdsaHVl0MXxojt7znsEwX6w3w7UqhFxerpFOk2Ivaxi2Gcy_QtHnqcaBW7jpaIbrolV8l1Q7z719V856muXtj-_fm1KvcsCKlH1sAmGg7JJ1NIrSV3gs9_qJiS8U5sOPepkFyK6L0rGh2MVsIYkSsvwDdSrsjDeTdgPwwYkz1he3A4WeB2QWIXJFYpuyCRf29EUsQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array</title><source>IOPscience journals</source><source>Institute of Physics:Jisc Collections:IOP Publishing Read and Publish 2024-2025 (Reading List)</source><creator>Kim, Hyun-Soo ; Yamamoto, Shuu'ichirou ; Ishikawa, Toru ; Fuchikami, Takaaki ; Ohki, Hiroshi ; Ishiwara, Hiroshi</creator><creatorcontrib>Kim, Hyun-Soo ; Yamamoto, Shuu'ichirou ; Ishikawa, Toru ; Fuchikami, Takaaki ; Ohki, Hiroshi ; Ishiwara, Hiroshi</creatorcontrib><description>A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 10 4 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 10 4 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.</description><identifier>ISSN: 0021-4922</identifier><identifier>EISSN: 1347-4065</identifier><identifier>DOI: 10.1143/JJAP.44.2715</identifier><language>eng</language><ispartof>Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2715</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33</citedby><cites>FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Kim, Hyun-Soo</creatorcontrib><creatorcontrib>Yamamoto, Shuu'ichirou</creatorcontrib><creatorcontrib>Ishikawa, Toru</creatorcontrib><creatorcontrib>Fuchikami, Takaaki</creatorcontrib><creatorcontrib>Ohki, Hiroshi</creatorcontrib><creatorcontrib>Ishiwara, Hiroshi</creatorcontrib><title>Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array</title><title>Japanese Journal of Applied Physics</title><description>A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 10 4 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 10 4 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.</description><issn>0021-4922</issn><issn>1347-4065</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><recordid>eNotkM1OwzAQhC0EEqFw4wH8ALh4_RM3xyiiQFUEh3C2bMcWgbSpNrmEpydROY1mpJnVfoTcA18DKPm425Ufa6XWwoC-IBlIZZjiub4kGecCmCqEuCY3w_A921wryMjn1nlsgxvb_kjdsaHVl0MXxojt7znsEwX6w3w7UqhFxerpFOk2Ivaxi2Gcy_QtHnqcaBW7jpaIbrolV8l1Q7z719V856muXtj-_fm1KvcsCKlH1sAmGg7JJ1NIrSV3gs9_qJiS8U5sOPepkFyK6L0rGh2MVsIYkSsvwDdSrsjDeTdgPwwYkz1he3A4WeB2QWIXJFYpuyCRf29EUsQ</recordid><startdate>20050401</startdate><enddate>20050401</enddate><creator>Kim, Hyun-Soo</creator><creator>Yamamoto, Shuu'ichirou</creator><creator>Ishikawa, Toru</creator><creator>Fuchikami, Takaaki</creator><creator>Ohki, Hiroshi</creator><creator>Ishiwara, Hiroshi</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20050401</creationdate><title>Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array</title><author>Kim, Hyun-Soo ; Yamamoto, Shuu'ichirou ; Ishikawa, Toru ; Fuchikami, Takaaki ; Ohki, Hiroshi ; Ishiwara, Hiroshi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kim, Hyun-Soo</creatorcontrib><creatorcontrib>Yamamoto, Shuu'ichirou</creatorcontrib><creatorcontrib>Ishikawa, Toru</creatorcontrib><creatorcontrib>Fuchikami, Takaaki</creatorcontrib><creatorcontrib>Ohki, Hiroshi</creatorcontrib><creatorcontrib>Ishiwara, Hiroshi</creatorcontrib><collection>CrossRef</collection><jtitle>Japanese Journal of Applied Physics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kim, Hyun-Soo</au><au>Yamamoto, Shuu'ichirou</au><au>Ishikawa, Toru</au><au>Fuchikami, Takaaki</au><au>Ohki, Hiroshi</au><au>Ishiwara, Hiroshi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array</atitle><jtitle>Japanese Journal of Applied Physics</jtitle><date>2005-04-01</date><risdate>2005</risdate><volume>44</volume><issue>4S</issue><spage>2715</spage><pages>2715-</pages><issn>0021-4922</issn><eissn>1347-4065</eissn><abstract>A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 10 4 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 10 4 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.</abstract><doi>10.1143/JJAP.44.2715</doi></addata></record>
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title Fabrication and Characterization of 1 k-bit 1T2C-Type Ferroelectric Memory Cell Array
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T01%3A47%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Fabrication%20and%20Characterization%20of%201%20k-bit%201T2C-Type%20Ferroelectric%20Memory%20Cell%20Array&rft.jtitle=Japanese%20Journal%20of%20Applied%20Physics&rft.au=Kim,%20Hyun-Soo&rft.date=2005-04-01&rft.volume=44&rft.issue=4S&rft.spage=2715&rft.pages=2715-&rft.issn=0021-4922&rft.eissn=1347-4065&rft_id=info:doi/10.1143/JJAP.44.2715&rft_dat=%3Ccrossref%3E10_1143_JJAP_44_2715%3C/crossref%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c235t-d18e701fbf7935530a201434eff7ba2800bf93032ebba9d5c754277264b21bd33%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true