Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

• Published in: Japanese Journal of Applied Physics 2011-05, Vol.50 (5), p.05ED02-05ED02-4
• Main Authors: Kitada, Hideki, Maeda, Nobuhide, Fujimoto, Koji, Mizushima, Yoriko, Nakata, Yoshihiro, Nakamura, Tomoji, Ohba, Takayuki
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.50.05ED02

Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density ${>}60$% of the bulk value and/or thickness ${>}100$ nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.