Effect of Dynamic Bias Stress in Short-Channel ($L=1.5$ μm) p-Type Polycrystalline Silicon Thin-Film Transistors

• Published in: Japanese Journal of Applied Physics 2012-02, Vol.51 (2), p.021401-021401-6
• Main Authors: Choi, Sung-Hwan, Mo, Yeon-Gon, Kim, Hye-Dong, Han, Min-Koo
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.51.021401

We have investigated the stability of short-channel (1.5 μm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel ($L=1.5$ μm) poly-Si TFT was increased by about $-7.44$ V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.