Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks

• Published in: ACM transactions on design automation of electronic systems 2022-12, Vol.28 (1), p.1-27, Article 3
• Main Authors: Chhabria, Vidya A., Ahuja, Vipul, Prabhu, Ashwath, Patil, Nikhil, Jain, Palkesh, Sapatnekar, Sachin S.
• Format: Article
• Language: English
• Subjects: Computing methodologies; Hardware; Neural networks; Physical design (EDA); Power grid design; Temperature simulation and estimation
• ISSN: 1084-4309; 1557-7309
• DOI: 10.1145/3526115

Power delivery network (PDN) analysis and thermal analysis are computationally expensive tasks that are essential for successful integrated circuit (IC) design. Algorithmically, both these analyses have similar computational structure and complexity as they involve the solution to a partial differential equation of the same form. This article converts these analyses into image-to-image and sequence-to-sequence translation tasks, which allows leveraging a class of machine learning models with an encoder-decoder–based generative (EDGe) architecture to address the time-intensive nature of these tasks. For PDN analysis, we propose two networks: (i) IREDGe: a full-chip static and dynamic IR drop predictor and (ii) EMEDGe: electromigration (EM) hotspot classifier based on input power, power grid distribution, and power pad distribution patterns. For thermal analysis, we propose ThermEDGe, a full-chip static and dynamic temperature estimator based on input power distribution patterns for thermal analysis. These networks are transferable across designs synthesized within the same technology and packing solution. The networks predict on-chip IR drop, EM hotspot locations, and temperature in milliseconds with negligibly small errors against commercial tools requiring several hours.