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Gross delay defect evaluation for a CMOS logic design system product

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Published in:	IBM journal of research and development 1990-03, Vol.34 (2-3), p.325-338
Main Authors:	BULA, O, MOSER, J, TRINKO, J, WEISSMAN, M, WOYTOWICH, F
Format:	Article
Language:	English
Subjects:	Applied sciences Electronics Exact sciences and technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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cited_by	cdi_FETCH-LOGICAL-c260t-d304cee10f92cc8b8c4bf1fbe9098858eb70184148c7e2c5fd1c2d65269978c43
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container_end_page	338
container_issue	2-3
container_start_page	325
container_title	IBM journal of research and development
container_volume	34
creator	BULA, O MOSER, J TRINKO, J WEISSMAN, M WOYTOWICH, F
description
doi_str_mv	10.1147/rd.342.0325
format	article
fullrecord	<record><control><sourceid>pascalfrancis_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1147_rd_342_0325</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>5543162</sourcerecordid><originalsourceid>FETCH-LOGICAL-c260t-d304cee10f92cc8b8c4bf1fbe9098858eb70184148c7e2c5fd1c2d65269978c43</originalsourceid><addsrcrecordid>eNo9kMFKxDAURYMoWEdX_kAW7qQ1SZM0WUrVURiZhbou6UsyVDptSTrC_L0pI27u3Zz3uByEbikpKOXVQ7BFyVlBSibOUMaooLkSQp6jjBCqciW5vERXMX4TQgTnOkNP6zDGiK3rzTGldzBj92P6g5m7ccB-DNjg-n37gftx10FCYrcbcDzG2e3xFEZ7gPkaXXjTR3fz1yv09fL8Wb_mm-36rX7c5MAkmXNbEg7OUeI1A1CtAt566luniVZKKNdWaSWnXEHlGAhvKTArBZNaVwkuV-j-9BeW0cH5Zgrd3oRjQ0mzCGiCbZKAZhGQ6LsTPZkIpvfBDNDF_xMheEklK38BeFBaVQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Gross delay defect evaluation for a CMOS logic design system product</title><source>IEEE Xplore All Journals</source><creator>BULA, O ; MOSER, J ; TRINKO, J ; WEISSMAN, M ; WOYTOWICH, F</creator><creatorcontrib>BULA, O ; MOSER, J ; TRINKO, J ; WEISSMAN, M ; WOYTOWICH, F</creatorcontrib><identifier>ISSN: 0018-8646</identifier><identifier>EISSN: 2151-8556</identifier><identifier>EISSN: 0018-8646</identifier><identifier>DOI: 10.1147/rd.342.0325</identifier><identifier>CODEN: IBMJAE</identifier><language>eng</language><publisher>Armonk, NY: International Business Machines</publisher><subject>Applied sciences ; Electronics ; Exact sciences and technology ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><ispartof>IBM journal of research and development, 1990-03, Vol.34 (2-3), p.325-338</ispartof><rights>1992 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c260t-d304cee10f92cc8b8c4bf1fbe9098858eb70184148c7e2c5fd1c2d65269978c43</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=5543162$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>BULA, O</creatorcontrib><creatorcontrib>MOSER, J</creatorcontrib><creatorcontrib>TRINKO, J</creatorcontrib><creatorcontrib>WEISSMAN, M</creatorcontrib><creatorcontrib>WOYTOWICH, F</creatorcontrib><title>Gross delay defect evaluation for a CMOS logic design system product</title><title>IBM journal of research and development</title><subject>Applied sciences</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0018-8646</issn><issn>2151-8556</issn><issn>0018-8646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNo9kMFKxDAURYMoWEdX_kAW7qQ1SZM0WUrVURiZhbou6UsyVDptSTrC_L0pI27u3Zz3uByEbikpKOXVQ7BFyVlBSibOUMaooLkSQp6jjBCqciW5vERXMX4TQgTnOkNP6zDGiK3rzTGldzBj92P6g5m7ccB-DNjg-n37gftx10FCYrcbcDzG2e3xFEZ7gPkaXXjTR3fz1yv09fL8Wb_mm-36rX7c5MAkmXNbEg7OUeI1A1CtAt566luniVZKKNdWaSWnXEHlGAhvKTArBZNaVwkuV-j-9BeW0cH5Zgrd3oRjQ0mzCGiCbZKAZhGQ6LsTPZkIpvfBDNDF_xMheEklK38BeFBaVQ</recordid><startdate>19900301</startdate><enddate>19900301</enddate><creator>BULA, O</creator><creator>MOSER, J</creator><creator>TRINKO, J</creator><creator>WEISSMAN, M</creator><creator>WOYTOWICH, F</creator><general>International Business Machines</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19900301</creationdate><title>Gross delay defect evaluation for a CMOS logic design system product</title><author>BULA, O ; MOSER, J ; TRINKO, J ; WEISSMAN, M ; WOYTOWICH, F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c260t-d304cee10f92cc8b8c4bf1fbe9098858eb70184148c7e2c5fd1c2d65269978c43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Applied sciences</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>BULA, O</creatorcontrib><creatorcontrib>MOSER, J</creatorcontrib><creatorcontrib>TRINKO, J</creatorcontrib><creatorcontrib>WEISSMAN, M</creatorcontrib><creatorcontrib>WOYTOWICH, F</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IBM journal of research and development</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>BULA, O</au><au>MOSER, J</au><au>TRINKO, J</au><au>WEISSMAN, M</au><au>WOYTOWICH, F</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Gross delay defect evaluation for a CMOS logic design system product</atitle><jtitle>IBM journal of research and development</jtitle><date>1990-03-01</date><risdate>1990</risdate><volume>34</volume><issue>2-3</issue><spage>325</spage><epage>338</epage><pages>325-338</pages><issn>0018-8646</issn><eissn>2151-8556</eissn><eissn>0018-8646</eissn><coden>IBMJAE</coden><cop>Armonk, NY</cop><pub>International Business Machines</pub><doi>10.1147/rd.342.0325</doi><tpages>14</tpages></addata></record>
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identifier	ISSN: 0018-8646
ispartof	IBM journal of research and development, 1990-03, Vol.34 (2-3), p.325-338
issn	0018-8646 2151-8556 0018-8646
language	eng
recordid	cdi_crossref_primary_10_1147_rd_342_0325
source	IEEE Xplore All Journals
subjects	Applied sciences Electronics Exact sciences and technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
title	Gross delay defect evaluation for a CMOS logic design system product
url	http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T23%3A27%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Gross%20delay%20defect%20evaluation%20for%20a%20CMOS%20logic%20design%20system%20product&rft.jtitle=IBM%20journal%20of%20research%20and%20development&rft.au=BULA,%20O&rft.date=1990-03-01&rft.volume=34&rft.issue=2-3&rft.spage=325&rft.epage=338&rft.pages=325-338&rft.issn=0018-8646&rft.eissn=2151-8556&rft.coden=IBMJAE&rft_id=info:doi/10.1147/rd.342.0325&rft_dat=%3Cpascalfrancis_cross%3E5543162%3C/pascalfrancis_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c260t-d304cee10f92cc8b8c4bf1fbe9098858eb70184148c7e2c5fd1c2d65269978c43%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true