Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions

• Published in: ECS transactions 2007-09, Vol.11 (3), p.47-53
• Main Authors: Bargallo Gonzalez, Mireia, Thomas, Nicole, Simoen, Eddy, Verheyen, Peter, Hikavyy, Andriy, Leys, Frederik, Okuno, Yasutoshi, Vissouvanadin Soubaretty, Bertrand, Van Daele, Benny, Geenen, Luc, Loo, Roger, Claeys, C., Machkaoutsan, Vladimir, Tomasini, Pierre, Thomas, Shawn, Ping Lu, Jiong, Weijtmans, J.W., Wise, Rick
• Format: Article
• Language: English
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/1.2778649

This paper reports on the impact of the pre-epi bake conditions on the epitaxial growth of Si1 xGex Source-Drain (S/D) stressors as studied by p-n junction leakage analysis. It has been demonstrated that the presence of impurity-related (O, C) defects located at the epi/substrate interface, can act as nucleation sites for misfit dislocations, which degrade device performance. It has been shown that the area current density decreases exponentially with the pre-epi bake temperature. An empirical approach has been developed to quantify the leakage current enhancement due to the formation of the impurity-related (O, C) defects present at the epi/substrate interface, when the pre-epi bake is insufficient to remove the interface contamination. Moreover, the impact of the waiting time before the loading of the wafer inside the reactor on the defect creation is discussed. Finally, it has been demonstrated experimentally that the study of p-n junction characteristics is a highly sensitive technique for the assessment of the quality of the epitaxial interface, when C and O levels at the epi/substrate interface approach the SIMS detection limits.