DC Performance and Low Frequency Noise in n-MOSFETs using Self-Aligned Poly-Si/SiGe Gate

• Main Authors: Jimenez Grados, Hugo R., Manera, Leandro T., Cotrin Teixeira, Ricardo, Rautemberg, Marcia, Diniz, José A., Doi, Ioshiaki, Tatsch, Peter Jurgen, Hernandes Figueroa, Hugo Enrique, Swart, Jacobus W.
• Format: Conference Proceeding
• Language: English
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/1.2956027

The characterization of an n-MOS transistor with poly-Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components (CCS) at UNICAMP is presented. The Gate layer was grown by vertical LPCVD at 800 {degree sign}C. The resultant transistor has a channel region with oxide thickness of 30 nm and self-aligned thick S/D region. The DC and Gm characteristics of poly-Si/SiGe n-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-to-source bias VDS of +0.1 V nMOSFETs with 3 µm gate length had peak transconductance (µS) increased as well, compared with conventional n-MOS with poly-Si gate. The Gm characteristics and low frequency noise 1/f of the n-MOS transistors are studied using devices sizes with width of 20 µm and several lengths. Promising devices for RF and microwave circuit applications, show low 1/f and high values of transconductance.