Inverted 'T' Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation

• Published in: ECS journal of solid state science and technology 2018-01, Vol.7 (4), p.Q52-Q59
• Main Authors: Vandana, B., Patro, B. S., Das, J. K., Kaushik, Brajesh Kumar, Mohapatra, S. K.
• Format: Article
• Language: English
• ISSN: 2162-8769; 2162-8769; 2162-8777
• DOI: 10.1149/2.0071804jss

The work explores the performance estimation of Inverted 'T' (IT) architecture with JL topology i.e (ITJL-FinFET, the device utilizes unwanted area among multi-fins with bulk conduction mechanism) on SOI platform. For the first time, the crucial performance metrics of ITJL FinFET are debated extensively by varying the geometry dimensions at 22-nm node. The gate length (LG), virtual underlap source (LUS) and drain (LUD), and workfunction (ϕM) are optimized at 20-nm, 4-nm, 4.6 eV respectively. The SS, DIBL and switching current ratio (ION/IOFF) are achieved 69 mV/decade, 27 mV/V and 105. The decrement in transconductance (gm) with increasing in length of LG, LUS, LUD and simultaniously, transconductance generation factor (TGF) tends to improve. Moreover, we have been examine the grid sensitivity of the device and considered the grid points where the independency of I-V characteristics achieved during simulation. The result ensures a systematic prefabrication analysis of ITJL FinFET found to be appropriate, which will overcome the challenges at the nanoscale regime.