Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

• Published in: VLSI Design 2012-01, Vol.2012 (2012), p.444-450
• Main Authors: Zhang, Zhen-dong, Wu, Bin, Zhou, Yu-mei, Zhang, Xin
• Format: Article
• Language: English
• ISSN: 1065-514X; 1563-5171
• DOI: 10.1155/2012/948957

A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm2, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.