A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers

• Published in: Frontiers of information technology & electronic engineering 2014-12, Vol.15 (12), p.1200-1210
• Main Authors: Guo, Ting, Li, Zhi-qun, Li, Qin, Wang, Zhi-gong
• Format: Article
• Language: English
• Subjects: Communications Engineering; Computer Hardware; Computer Science; Computer Systems Organization and Communication Networks; Electrical Engineering; Electronics and Microelectronics; Frequency dividers; Frequency ranges; Frequency synthesizers; Instrumentation; Millimeter waves; Networks; Phase locked loops; Phase noise; Prescalers; Pulse counters; Synthesizers
• ISSN: 1869-1951; 2095-9184; 1869-196X; 2095-9230
• DOI: 10.1631/jzus.C1400091

A 37 GHz wide-band programmable divide-by-N frequency divider （FD） composed of a divide-by-2 divider （acting as the first stage） and a divider with a division ratio range of 273 330 （acting as the second stage） has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider （with high speed） and the divide-by-8/9 prescaler employ dynamic current-mode logic （DCML） structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as 20 dBm at 32 GHz and the phase noise at 37 GHz is less than -130 dBc/Hz at an offset of 1MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730μm ×475 μm.