Design of Multiplier through Modified Booth Algorithm with Mig Gate

• Published in: International journal of innovative technology and exploring engineering 2019-12, Vol.9 (2), p.3101-3105
• Main Authors: Gurava, Ripunjai, babu, P. Suresh
• Format: Article
• Language: English
• ISSN: 2278-3075; 2278-3075
• DOI: 10.35940/ijitee.B7476.129219

This paper compares different Booth multipliers i.e., Radix-2, 4, 8 is designed using a new carry look-Ahead adder (CLA). In this Delay and Power have been compared and the main aim behind the project is developing Booth multiplier using Reversible Logic Gate (RLG).While comparing with the normal multiplication, Modified Booth Algorithm gives the less amount of delay as the number of partial products gets reduced. In this process CLA is used to reduce the overall multiplier Delay.The reversible logic is considered because it reduces the circuit complexity, loss of information and power consumption. In this paper a new CLA architecture is proposed in place of the existing CLA architecture which exhibits a high performance of computation, power consumption and area. In this architecture, Delay and power consumption of the design are reported. This new architecture is simulated and synthesized using Xilinx ISE environment.