Full Adder for Low Power Applications

• Published in: International journal of innovative technology and exploring engineering 2020-02, Vol.9 (4), p.2612-2687
• Main Authors: Jhamb, Dr. Mansi, Kumar, Manoj, Vishal
• Format: Article
• Language: English
• ISSN: 2278-3075; 2278-3075
• DOI: 10.35940/ijitee.D1846.029420

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.