Implementation and Utilization of LBIST for 16 bit ALU

• Published in: International journal of innovative technology and exploring engineering 2019-08, Vol.8 (10), p.1915-1920
• Main Authors: Warade, Nilima, Ravi, T.
• Format: Article
• Language: English
• ISSN: 2278-3075; 2278-3075
• DOI: 10.35940/ijitee.J9266.0881019

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.