Synthetic Benchmark Digital Circuits: A Survey

Today's VLSI CAD tools are to be designed to handle tomorrow's designs. But, what are tomorrow's designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware arc...

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Bibliographic Details
Published in:Technical review - IETE 2012-11, Vol.29 (6), p.442-448
Main Authors: Srivani, L., Kamakoti, Veezhinathan
Format: Article
Language:English
Subjects:
Architects
Architecture
Automation
Benchmarks
Computer-aided design tools
Field programmable gate arrays
Software
Studies
Synthetic benchmark circuits
Very large-scale integration
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Summary:Today's VLSI CAD tools are to be designed to handle tomorrow's designs. But, what are tomorrow's designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.
ISSN:0256-4602
0974-5971
DOI:10.4103/0256-4602.104999