A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop

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Published in:International journal of computer applications 2012-02, Vol.39 (18), p.62-67
Main Authors: KumarB.V.P, Vasantha, S. Murthy Sharma, N., Lal Kishore, K.
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Language:English
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container_issue 18
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container_title International journal of computer applications
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creator KumarB.V.P, Vasantha
S. Murthy Sharma, N.
Lal Kishore, K.
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doi_str_mv 10.5120/5086-7450
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title A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop
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