Design Feasibility of High-Performance Si Wire Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistor in Sub-30-nm-Channel Regime

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2011-01, Vol.50 (1R), p.14201
Main Author: Omura, Yasuhisa
Format: Article
Language:eng ; jpn
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ISSN:0021-4922
1347-4065
DOI:10.7567/JJAP.50.014201