Effectiveness of hybrid recovery techniques on parametric failures

• Main Authors: Ganapathy, S., Canal, R., Gonzalez, A., Rubio, A.
• Format: Conference Proceeding
• Language: English
• Subjects: Boosting; Cache storage; Circuits integrats; Enginyeria electrònica; Failure analysis; Hafnium; Integrated circuit reliability; Integrated circuits; Microelectrònica; Probability; Redundancy; SRAM cells; Threshold voltage; Transistors; Àrees temàtiques de la UPC
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2013.6523620

Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V dd min . On-chip memories like caches are the most susceptible to voltage-noise induced failures because of process variations and reduced noise-margins thereby arbitrating whole processor's V dd min . In this paper, we evaluate the effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Proactive read/write assist techniques like body-biasing (BB) and wordline boosting (WLB) when combined with reactive techniques like ECC and redundancy are shown to offer better quality-energy-area trade offs when compared to their standalone configurations. Proactive techniques can help lower V dd min (improving functional margin) for significant power savings and reactive techniques ensure that the resulting large number of failures are corrected (improving functional yield). Our results in 22nm technology indicate that at scaled supply voltages, hybrid techniques can improve parametric yield by atleast 28% when considering worst-case process variations.