Delaying physical register allocation trought virtual-physical registers

• Main Authors: Monreal Arnal, Teresa, González Colás, Antonio María, Valero Cortés, Mateo, González González, José, Viñals Yufera, Víctor
• Format: Text Resource
• Language: English
• Subjects: Arquitectura de computadors; Delays; Informàtica; Microprocessadors; Microprocessors; Parallel processing; Parallel processing (Electronic computers); Performance evaluation; Processament en paral·lel (Ordinadors); Storage management; Àrees temàtiques de la UPC
• DOI: 10.1109/MICRO.1999.809456

Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper presents a novel physical register management scheme that allows for a late allocation (at the end of execution) of registers. We show that it can provide significant savings in number of registers and thus, it can significantly shorten the register file access time. The approach is based on virtual-physical registers, which we presented in a previous work, extended with a new register allocation policy. This policy consists of an on-demand allocation in order to maximize the register usage, combined with a stealing mechanism that prevents older instruction from being delayed by younger ones. This shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance. Peer Reviewed