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Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors
The introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts to become one of the most promising ways to improve the system performance. How...
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Published in: | IEEE transactions on parallel and distributed systems 2013-12, Vol.24 (12), p.2513-2525 |
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container_title | IEEE transactions on parallel and distributed systems |
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creator | Radojkovic, Petar Cakarevic, Vladimir Verdu, Javier Pajuelo, Alex Cazorla, Francisco J. Nemirovsky, Mario Valero, Mateo |
description | The introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts to become one of the most promising ways to improve the system performance. However, finding optimal thread assignments for workloads running in state-of-the-art multicore/multithreaded processors is an NP-complete problem. In this paper, we propose BlackBox scheduler, a systematic method for thread assignment of multithreaded network applications running on multicore/multithreaded processors. The method requires minimum information about the target processor architecture and no data about the hardware requirements of the applications under study. The proposed method is evaluated with an industrial case study for a set of multithreaded network applications running on the UltraSPARC T2 processor. In most of the experiments, the proposed thread assignment method detected the best actual thread assignment in the evaluation sample. The method improved the system performance from 5 to 48 percent with respect to load balancing algorithms used in state-of-the-art OSs, and up to 60 percent with respect to a naive thread assignment. |
doi_str_mv | 10.1109/TPDS.2012.311 |
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The method improved the system performance from 5 to 48 percent with respect to load balancing algorithms used in state-of-the-art OSs, and up to 60 percent with respect to a naive thread assignment.</description><subject>Arquitectura de computadors</subject><subject>Chip multithreading (CMT)</subject><subject>Informàtica</subject><subject>Instruction sets</subject><subject>Interference</subject><subject>Message systems</subject><subject>Multiprocessadors</subject><subject>Multiprocessors</subject><subject>Multithread processing</subject><subject>Performance modeling</subject><subject>Process scheduling</subject><subject>Resource management</subject><subject>Simultaneous multithreading processors</subject><subject>Àrees temàtiques de la UPC</subject><issn>1045-9219</issn><issn>1558-2183</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><recordid>eNpVkN9LAzEMx4soOKePPvly_8BtTX_cro_D3zB14HyUUttUq9t1tDfE_947NxQhIQn5JCRfQk6BjgCoGi_mF48jRoGNOMAeGYCUdcmg5vtdToUsFQN1SI5yfqcUhKRiQJ4XbwmNK6Y5h9dmhU1bRF_cbZZtaH866Ip7bD9j-iim6_UyWNOG2OQiNFvKxoTj__w8RYs5x5SPyYE3y4wnuzgkT1eXi_ObcvZwfXs-nZWW87otDbw4VytlveOW1bU1VEwYkxS5Z6qWznljOzNQCS8AHFKPlVNOIFTSCT4ksN1r88bqhBZTd6eOJvwVvTM6YZopAEG7mXI3k2LOCb1ep7Ay6UsD1b2eutdT93rqTs-OP9vyARF_2ap7gEnBvwHs9HPk</recordid><startdate>20131201</startdate><enddate>20131201</enddate><creator>Radojkovic, Petar</creator><creator>Cakarevic, Vladimir</creator><creator>Verdu, Javier</creator><creator>Pajuelo, Alex</creator><creator>Cazorla, Francisco J.</creator><creator>Nemirovsky, Mario</creator><creator>Valero, Mateo</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>XX2</scope></search><sort><creationdate>20131201</creationdate><title>Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors</title><author>Radojkovic, Petar ; Cakarevic, Vladimir ; Verdu, Javier ; Pajuelo, Alex ; Cazorla, Francisco J. ; Nemirovsky, Mario ; Valero, Mateo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c338t-a1bdd899cfd3c288ca0472250e3f2985ddfacfaca164f411de0fe6d9d4e165d43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Arquitectura de computadors</topic><topic>Chip multithreading (CMT)</topic><topic>Informàtica</topic><topic>Instruction sets</topic><topic>Interference</topic><topic>Message systems</topic><topic>Multiprocessadors</topic><topic>Multiprocessors</topic><topic>Multithread processing</topic><topic>Performance modeling</topic><topic>Process scheduling</topic><topic>Resource management</topic><topic>Simultaneous multithreading processors</topic><topic>Àrees temàtiques de la UPC</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Radojkovic, Petar</creatorcontrib><creatorcontrib>Cakarevic, Vladimir</creatorcontrib><creatorcontrib>Verdu, Javier</creatorcontrib><creatorcontrib>Pajuelo, Alex</creatorcontrib><creatorcontrib>Cazorla, Francisco J.</creatorcontrib><creatorcontrib>Nemirovsky, Mario</creatorcontrib><creatorcontrib>Valero, Mateo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Recercat</collection><jtitle>IEEE transactions on parallel and distributed systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Radojkovic, Petar</au><au>Cakarevic, Vladimir</au><au>Verdu, Javier</au><au>Pajuelo, Alex</au><au>Cazorla, Francisco J.</au><au>Nemirovsky, Mario</au><au>Valero, Mateo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors</atitle><jtitle>IEEE transactions on parallel and distributed systems</jtitle><stitle>TPDS</stitle><date>2013-12-01</date><risdate>2013</risdate><volume>24</volume><issue>12</issue><spage>2513</spage><epage>2525</epage><pages>2513-2525</pages><issn>1045-9219</issn><eissn>1558-2183</eissn><coden>ITDSEO</coden><abstract>The introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts to become one of the most promising ways to improve the system performance. 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subjects | Arquitectura de computadors Chip multithreading (CMT) Informàtica Instruction sets Interference Message systems Multiprocessadors Multiprocessors Multithread processing Performance modeling Process scheduling Resource management Simultaneous multithreading processors Àrees temàtiques de la UPC |
title | Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors |
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