Analysis of bias stress on thin-film transistors obtained by Hot-Wire Chemical Vapour Deposition

The stability under gate bias stress of unpassivated thin film transistors was studied by measuring the transfer and output characteristics at different temperatures. The active layer of these devices consisted of in nanocrystalline silicon deposited at 125°C by Hot-Wire Chemical Vapour Deposition....

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Main Authors: Dosev, D K, Puigdollers i González, Joaquim, Orpella García, Alberto, Voz Sánchez, Cristóbal, Fonrodona, Marta, Soler Vilamitjana, David, Marsal, L F, Pallarès Marzal, Josep, Bertomeu Balaguero, Joan, Andreu Batallé, Jordi, Alcubilla González, Ramón
Format: Text Resource
Language:English
Subjects:
Física
Física de l'estat sòlid
HWCVD
Nanocrystalline silicon
Solid state physics
Stability
TFT
Àrees temàtiques de la UPC
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Summary:The stability under gate bias stress of unpassivated thin film transistors was studied by measuring the transfer and output characteristics at different temperatures. The active layer of these devices consisted of in nanocrystalline silicon deposited at 125°C by Hot-Wire Chemical Vapour Deposition. The dependence of the subthreshold activation energy on gate bias for different gate bias stresses is quite different from the one reported for hydrogenated amorphous silicon. This behaviour has been related to trapped charge in the active layer of the thin film transistor. Peer Reviewed
ISSN:0040-6090
DOI:10.1016/S0040-6090(00)01608-4