Experimental time evolution study of the HFO-based IMPLY gate operation

• Main Authors: Maestro, M, Marin-Martinez, J, Crespo-Yepes, A, Escudero, Manel, Rodriguez, R, Nafria, M, Aymerich, X, Rubio Sola, Jose Antonio
• Format: Text Resource
• Language: English
• Subjects: Circuits electrònics; Electrodes; Electronic circuits; Elèctrodes; Enginyeria electrònica; IMPLY; logic; Material Implication; memristors; Resistive Switching; Àrees temàtiques de la UPC
• ISSN: 0018-9383
• DOI: 10.1109/TED.2017.2778315

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated but most of the efforts have been just focused on accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is still missing and barely reported yet. In this work, the time evolution of memristor involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included. Peer Reviewed