Evaluation of A+B=K conditions without carry propagation

The response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that it can be evaluated without carry propagation, thus drastically reducing the com...

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Bibliographic Details
Published in:IEEE transactions on computers 1992-11, Vol.41 (11), p.1484-1488
Main Authors: Cortadella, J., Llaberia, J.M.
Format: Article
Language:English
Subjects:
Adders
Applied sciences
Arquitectura de computadors
Arquitectures paral·leles
Circuits
Circuits lògics
Computer aided instruction
Computer architecture
Computer science
control theory
systems
Computer systems and distributed systems. User interface
Delay effects
Equations
Exact sciences and technology
Frequency
Hazards
Informàtica
Logic circuits
Performance evaluation
Reduced instruction set computing
Software
Àrees temàtiques de la UPC
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Summary:The response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that it can be evaluated without carry propagation, thus drastically reducing the computation time. Dependencies produced by branches degrade the performance of pipelined computers. The evaluation of conditions is often one of the critical paths in the execution of branch instructions. A circuit is proposed for the fast evaluation of A+B=K conditions that can significantly improve processor performance.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.177318