Quantum conductance staircase of holes in silicon nanosandwiches

• Published in: Modern electronic materials 2017-03, Vol.3 (1), p.40-49
• Main Authors: Bagraev, Nikolay T., Khromov, V.S., Klyachkin, Leonid E., Malyarenko, Anna M.
• Format: Article
• Language: English
• Subjects: Edge channels; Odd and even fractional values; Quantum conductance staircase; Silicon nanosandwich
• ISSN: 2452-1779; 2452-1779
• DOI: 10.1016/j.moem.2017.04.003

The results of studying the quantum conductance staircase of holes in one-dimensional channels obtained by the split-gate method inside silicon nanosandwiches that are the ultra-narrow quantum well confined by the delta barriers heavily doped with boron on the n-type Si (100) surface are reported. Since the silicon quantum wells studied are ultra-narrow (~2nm) and confined by the delta barriers that consist of the negative-U dipole boron centers, the quantized conductance of one-dimensional channels is observed at relatively high temperatures (T>77K). Further, the current-voltage characteristic of the quantum conductance staircase is studied in relation to the kinetic energy of holes and their sheet density in the quantum wells. The results show that the quantum conductance staircase of holes in p-Si quantum wires is caused by independent contributions of the one-dimensional (1D) subbands of the heavy and light holes. In addition, the field-related inhibition of the quantum conductance staircase is demonstrated in the situation when the energy of the field-induced heating of the carriers become comparable to the energy gap between the 1D subbands. The use of the split-gate method made it possible to detect the effect of a drastic increase in the height of the quantum conductance steps when the kinetic energy of holes is increased; this effect is most profound for quantum wires of finite length, which are not described under conditions of a quantum point contact. In the concluding section of this paper we present the findings for the quantum conductance staircase of holes that is caused by the edge channels in the silicon nanosandwiches prepared within frameworks of the Hall geometry. This longitudinal quantum conductance staircase, Gxx, is revealed by the voltage applied to the Hall contacts, with the plateaus and steps that bring into correlation respectively with the odd and even fractional values.