Critical Gates Identification for Fault-Tolerant Design in Math Circuits

Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this p...

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Bibliographic Details
Published in:Journal of electrical and computer engineering 2017-01, Vol.2017 (2017), p.1-7
Main Authors: Ban, Tian, Junior, Gutemberg G. S.
Format: Article
Language:English
Subjects:
Circuit design
Circuits
Design
Design engineering
Efficiency
Error detection
Fault tolerance
Gates (circuits)
Redundancy
Transistors
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Summary:Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.
ISSN:2090-0147
2090-0155
DOI:10.1155/2017/5684902