Verification methods for complex-functional blocks in CAD for chips deep submicron design standards

The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice...

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Bibliographic Details
Published in:E3S Web of Conferences 2023-01, Vol.376, p.1090
Main Authors: Zolnikov, Vladimir, Zolnikov, Konstantin, Ilina, Nadezhda, Grabovy, Kirill
Format: Article
Language:English
Subjects:
Circuit design
Design standards
Integrated circuits
Verification
Very large scale integration
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Summary:The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.
ISSN:2267-1242
2555-0403
2267-1242
DOI:10.1051/e3sconf/202337601090