A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

• Published in: EURASIP journal on advances in signal processing 2020-11, Vol.2020 (1), p.1-9, Article 48
• Main Authors: Chen, Yuan-Ho, Liu, Chieh-Yang
• Format: Article
• Language: English
• Subjects: CMOS; Coding; Complementary metal oxide semiconductors; Discrete cosine transform; Engineering; Gate counting; High-efficiency video coding (HEVC); Image coding; Integrated circuit fabrication; Integrated circuits; Inverse discrete cosine transform (IDCT); Mathematical analysis; Matrix methods; Multiple transform dimensions; Quantum Information Technology; Shift-and-add unit (SAU); Signal,Image and Speech Processing; Small area; Spintronics; Time sharing; Very large scale integration; Very-large-scale integration (VLSI)
• ISSN: 1687-6180; 1687-6172; 1687-6180
• DOI: 10.1186/s13634-020-00708-0

In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.