PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers

An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ens...

Full description

Saved in:
Bibliographic Details
Published in:Applied sciences 2020-05, Vol.10 (9), p.3131
Main Authors: Kim, Kyungho, Choi, Seungju, Kwon, Hyeokdong, Kim, Hyunjun, Liu, Zhe, Seo, Hwajeong
Format: Article
Language:English
Subjects:
AES
Algorithms
Cryptography
Data encryption standards
Evaluation
fast software encryption
Galois Counter Mode of operation
Innovations
Internet of Things
low-end microcontrollers
Methods
Microcontrollers
Microprocessors
Optimization
RISC
Safety and security measures
Security
side channel attack countermeasure
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ensures constant timing. The main idea is replacing expensive AES operations, including AddRound Key, SubBytes, ShiftRows, and MixColumns, into simple look-up table access. Unlike previous works, the look-up table does not require look-up table updates during the entire encryption life-cycle. Second, the core operation of Galois Counter Mode (GCM) is optimized further by using Karatsuba algorithm, compact register utilization, and pre-computed operands. With above optimization techniques, proposed AES-GCM on 8-bit AVR (Alf and Vegard’s RISC processor) architecture from short-term, middle-term to long-term security levels achieved 415, 466, and 477 clock cycles per byte, respectively.
ISSN:2076-3417
2076-3417
DOI:10.3390/app10093131