Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

• Published in: East European journal of physics 2024-01 (1), p.417-425
• Main Authors: Messai, Zitouni, Brahimi, Abdelhalim, Saidani, Okba, Bourouba, Nacerdine, Yousfi, Abderrahim
• Format: Article
• Language: English
• Subjects: channels dimensions; cmos; pspice; temperature
• ISSN: 2312-4334; 2312-4539
• DOI: 10.26565/2312-4334-2024-1-44

This paper presents the impact of temperature variations and alterations in transistor channel dimensions on CMOS (Complementary Metal-Oxide-Semiconductor) circuit technology. To facilitate this investigation, we first identified critical parameters characterizing the device's performance, which could exhibit susceptibility to these influences. The analysis encompassed critical metrics such as the transfer characteristic, drain current, logic levels, inflection points, and truncation points. These parameters enabled us to validate the results obtained from the PSPICE simulator, which demonstrated unequivocal effectiveness. Notably, our simulation results unveiled significant effects resulting from a wide temperature range spanning from -100°C to 270°C, offering valuable in-sights into thermal-induced failures. Additionally, the influence of channel dimension changes on factors like drain current and transfer characteristics, as well as temporal parameters including signal propagation delay and rise and fall times, were meticulously examined and appreciated.