Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are th...

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Bibliographic Details
Published in:Scientific reports 2024-04, Vol.14 (1), p.8492-8492, Article 8492
Main Authors: Thamizharasan, V., Parthipan, V.
Format: Article
Language:English
Subjects:
639/166
639/705
Compressor
Cryptography
Digital signal processors
Field programmable gate array (FPGA)
Field programmable gate arrays
Humanities and Social Sciences
Hybrid
Image processing
Mathematics
multidisciplinary
Multiplier
Science
Science (multidisciplinary)
Signal processing
Spartan6
Xilinx
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Summary:In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).
ISSN:2045-2322
2045-2322
DOI:10.1038/s41598-024-58482-0