Cascade and Extensible In-Memory Arithmetic Computing in 2T1R ReRAM Arrays Using Time-Sum-Logic Design

• Published in: IEEE access 2024, Vol.12, p.104081-104090
• Main Authors: Zhu, Wei, He, Yi-Xing, Li, Hao-Nan, Liu, Xian-Qin, Zhang, Siwen, Wang, Lei, Zhu, Jiang, Wang, Yue-Qi, Zhang, Jincheng, Hao, Yue, Ma, Haijiao Harsan
• Format: Article
• Language: English
• Subjects: Adding circuits; Arithmetic; arithmetic computing; Arrays; Circuits; Computation; Computer memory; crossbar; Delays; Design; Extensibility; In-memory computing; Logic; Logic design; Memristor; Memristors; Multipliers; Pipelines; Resistance; Transistors
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3431206

Many designs of in-memory logic computing using ReRAM have been proposed and even a few of them have been experimentally demonstrated. However, the ability to cascade and extend the designed circuits is limited. In this work, we elaborate a design called time-sum-logic based on 2T1R memristor arrays and implement arithmetic computing circuits using memristors by integrating both time and space dimension. The core method of our design is to use sum of minterms to transfer logic to time sequence by 2T1R memristor arrays. This method is extensible by extending the number of layers to realize multi-bit arithmetic computing. Remarkably, cascading between different layers is elaborated carefully and pipelines are adopted to manage the sequence of memristors' writing and reading and lower the complexity and latency. In this way, the proposed circuits will be more efficient and can support high data throughout. Based on our design, 4-bit full adder and 4\times 4 multiplier are designed with pipelines, and n-bit full adders and m \times n multipliers could be easily constructed. The low latency and high efficiency confirm the advantages we have illustrated and show a promised application prospect.