Adaptive FPGA-Based Accelerators for Human-Robot Interaction in Indoor Environments

• Published in: Sensors (Basel, Switzerland) Switzerland), 2024-10, Vol.24 (21), p.6986
• Main Authors: Sravanthi, Mangali, Gunturi, Sravan Kumar, Chinnaiah, Mangali Chinna, Lam, Siew-Kei, Vani, G Divya, Basha, Mudasar, Janardhan, Narambhatla, Krishna, Dodde Hari, Dubey, Sanjay
• Format: Article
• Language: English
• Subjects: Algorithms; Automation; Consumption; Data collection; Digital integrated circuits; Efficiency; Field programmable gate arrays; FPGA; Humans; Internet of Things; Localization; Medicine; Optimization techniques; Posture - physiology; posture recognition; Robotics; Robotics - methods; Robotics industry; Robots; sensor fusion; Sensors; service robot; Sleep
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s24216986

This study addresses the challenges of human-robot interactions in real-time environments with adaptive field-programmable gate array (FPGA)-based accelerators. Predicting human posture in indoor environments in confined areas is a significant challenge for service robots. The proposed approach works on two levels: the estimation of human location and the robot's intention to serve based on the human's location at static and adaptive positions. This paper presents three methodologies to address these challenges: binary classification to analyze static and adaptive postures for human localization in indoor environments using the sensor fusion method, adaptive Simultaneous Localization and Mapping (SLAM) for the robot to deliver the task, and human-robot implicit communication. VLSI hardware schemes are developed for the proposed method. Initially, the control unit processes real-time sensor data through PIR sensors and multiple ultrasonic sensors to analyze the human posture. Subsequently, static and adaptive human posture data are communicated to the robot via Wi-Fi. Finally, the robot performs services for humans using an adaptive SLAM-based triangulation navigation method. The experimental validation was conducted in a hospital environment. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed-board-based FPGA Xilinx board was used for experimental validation.