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Maximizing Utilization and Minimizing Migration in Thermal-Aware Energy-Efficient Real-Time Multiprocessor Scheduling
This work proposes CAlECs, a clustered scheduling system for MPSoCs subject to thermal and energy constraints. It calculates off-line a cyclic executive honoring temporal and thermal constraints, for a hard real-time (HRT) task set at minimum frequency to reduce consumed energy, minimizing context s...
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Published in: | IEEE access 2021, Vol.9, p.83309-83328 |
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description | This work proposes CAlECs, a clustered scheduling system for MPSoCs subject to thermal and energy constraints. It calculates off-line a cyclic executive honoring temporal and thermal constraints, for a hard real-time (HRT) task set at minimum frequency to reduce consumed energy, minimizing context switches and migrations. It also provides an on-line controller able to manage system and task parametric variations and soft real-time (SRT) tasks, always meeting the HRT task set constraints and the system thermal bound. CAlECS maximizes CPU utilization to help avoid overprovisioning contributing to a low SWaP factor. Its modular design allows the utilization of different modeling and scheduling approaches, and makes the off-line and on-line components independent from each other to better suit the requirements of a specific system. We experimentally show that the cyclic executive provided by CAlECS for HRT task sets outperforms RUN, a reference off-line algorithm in terms of optimal number of context switches. |
doi_str_mv | 10.1109/ACCESS.2021.3086698 |
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It calculates off-line a cyclic executive honoring temporal and thermal constraints, for a hard real-time (HRT) task set at minimum frequency to reduce consumed energy, minimizing context switches and migrations. It also provides an on-line controller able to manage system and task parametric variations and soft real-time (SRT) tasks, always meeting the HRT task set constraints and the system thermal bound. CAlECS maximizes CPU utilization to help avoid overprovisioning contributing to a low SWaP factor. Its modular design allows the utilization of different modeling and scheduling approaches, and makes the off-line and on-line components independent from each other to better suit the requirements of a specific system. We experimentally show that the cyclic executive provided by CAlECS for HRT task sets outperforms RUN, a reference off-line algorithm in terms of optimal number of context switches.</description><identifier>ISSN: 2169-3536</identifier><identifier>EISSN: 2169-3536</identifier><identifier>DOI: 10.1109/ACCESS.2021.3086698</identifier><identifier>CODEN: IAECCG</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Algorithms ; clustering algorithms ; Context ; control ; Design factors ; Job shop scheduling ; Modular design ; Multiprocessing ; multiprocessors ; Optimization ; Partitioning algorithms ; Petri nets ; Processor scheduling ; Real time ; Real-time systems ; Schedules ; Scheduling ; Switches ; Task analysis ; Utilization</subject><ispartof>IEEE access, 2021, Vol.9, p.83309-83328</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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We experimentally show that the cyclic executive provided by CAlECS for HRT task sets outperforms RUN, a reference off-line algorithm in terms of optimal number of context switches.</description><subject>Algorithms</subject><subject>clustering algorithms</subject><subject>Context</subject><subject>control</subject><subject>Design factors</subject><subject>Job shop scheduling</subject><subject>Modular design</subject><subject>Multiprocessing</subject><subject>multiprocessors</subject><subject>Optimization</subject><subject>Partitioning algorithms</subject><subject>Petri nets</subject><subject>Processor scheduling</subject><subject>Real time</subject><subject>Real-time systems</subject><subject>Schedules</subject><subject>Scheduling</subject><subject>Switches</subject><subject>Task analysis</subject><subject>Utilization</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>DOA</sourceid><recordid>eNpNUU1r20AQFSWFhtS_wBdBz3L2W7tHY9w0YFOo7fOyWs3aY2QpXUmkya_PukpD5zLDvHlvZnhZNqdkQSkx98vVar3bLRhhdMGJVsroT9kto8oUXHJ181_9JZv1_Zmk0Kkly9ts3Lo_eMFXbI_5YcAGX92AXZu7ts632P6DtniME4Btvj9BvLimWD67CPm6hXh8KdYhoEdoh_wXJGyPF8i3YzPgU-w89H0X850_QT02Se9r9jm4pofZe77LDt_X-9WPYvPz4XG13BReED0U3kDlvFRSEq54EIaTitdEOsW8FExLAd774JnRStTBaCGZpMQpFRQzPvC77HHSrTt3tk8RLy6-2M6h_dvo4tG6OKBvwDIFZcUdrzkTwhFR1bwGxipCK82Npknr26SVHvo9Qj_YczfGNp1vmRRUKFXSMk3xacrHru8jhI-tlNirXXayy17tsu92JdZ8YiEAfDCMECXhJX8DVYqRoA</recordid><startdate>2021</startdate><enddate>2021</enddate><creator>Rubio-Anguiano, Laura Elena</creator><creator>Trabanco, Abel Chils</creator><creator>Velasco, Jose Luis Briz</creator><creator>Ramirez-Trevino, Antonio</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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subjects | Algorithms clustering algorithms Context control Design factors Job shop scheduling Modular design Multiprocessing multiprocessors Optimization Partitioning algorithms Petri nets Processor scheduling Real time Real-time systems Schedules Scheduling Switches Task analysis Utilization |
title | Maximizing Utilization and Minimizing Migration in Thermal-Aware Energy-Efficient Real-Time Multiprocessor Scheduling |
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