An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a fiel...

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Bibliographic Details
Published in:Journal of electrical and computer engineering 2014-01, Vol.2014 (2014), p.1-5
Main Authors: Fang, Guangyou, Xia, Zhenghuan, Meng, Shengwei, Chen, Chao, Yin, Hejun
Format: Article
Language:English
Subjects:
Conversion
Converters
Delay
Delay lines
Equivalence
Field programmable gate arrays
Oscillators
R&D
Research & development
Tables (data)
Technological change
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Summary:We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a field programmable gate array (FPGA) device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT) generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.
ISSN:2090-0147
2090-0155
DOI:10.1155/2014/230803