A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures

This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical-thermal working condit...

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Bibliographic Details
Published in:Micromachines (Basel) 2024-06, Vol.15 (6), p.772
Main Authors: Liu, Li, Guo, Jingqi, Shi, Yiheng, Zeng, Kai, Li, Gangpeng
Format: Article
Language:English
Subjects:
Circuit components
Degradation
Electric properties
Energy
failure analysis
Failure mechanisms
Field effect transistors
Metal oxide semiconductor field effect transistors
Metal oxide semiconductors
MOSFETs
optimized structure
Parameters
Semiconductor devices
SiC trench power MOSFET
Silicon carbide
UIS
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Summary:This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical-thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters' degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.
ISSN:2072-666X
2072-666X
DOI:10.3390/mi15060772