Managing contamination delay to improve Timing Speculation architectures

Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking fo...

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Bibliographic Details
Published in:PeerJ. Computer science 2016-08, Vol.2, p.e79, Article e79
Main Authors: Avirneni, Naga Durga Prasad, Ramesh, Prem Kumar, Somani, Arun K
Format: Article
Language:English
Subjects:
Algorithms
Automation
Circuits
Contamination
Critical path
Delay
Delay insertion
Electronic design automation
Impact analysis
International conferences
Overclocking
Performance enhancement
Propagation
PVT variation
System effectiveness
Timing constraints
Timing errors
Timing speculation
Violations
Citations: Items that this one cites
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Summary:Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.
ISSN:2376-5992
2376-5992
DOI:10.7717/peerj-cs.79