Design and Characterization of Semi-Floating-Gate Synaptic Transistor

• Published in: Micromachines (Basel) 2019-01, Vol.10 (1), p.32
• Main Authors: Cho, Yongbeom, Lee, Jae Yoon, Yu, Eunseon, Han, Jae-Hee, Baek, Myung-Hyun, Cho, Seongjae, Park, Byung-Gook
• Format: Article
• Language: English
• Subjects: Artificial intelligence; Bias; Efficiency; Electric fields; Field effect transistors; highly miniaturized transistor structure; low power consumption; neuromorphic system; Polysilicon; Power consumption; semi-floating gate; Semiconductor devices; Simulation; spike-timing-dependent plasticity (STDP); Spikes; synaptic transistor; Transistors
• ISSN: 2072-666X; 2072-666X
• DOI: 10.3390/mi10010032

In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler⁻Nordheim tunneling mechanism. Moreover, since the SFG is charged by an embedded tunneling field-effect transistor existing between the channel and the drain junction when the post-synaptic spike occurs after the pre-synaptic spike, and vice versa, the SFG is discharged by the diode when the post-synaptic spike takes place before the pre-synaptic spike. This indicates that the SFGST can attain STP/LTP and spike-timing-dependent plasticity behaviors. These characteristics of the SFGST in the highly miniaturized transistor structure can contribute to the neuromorphic chip such that the total system may operate as fast as the human brain with low power consumption and high integration density.