Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device character...

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Bibliographic Details
Published in:Sensors (Basel, Switzerland) Switzerland), 2021-09, Vol.21 (18), p.6074
Main Authors: Souilem, Malek, Tripathi, Jai Narayan, Melicio, Rui, Dghais, Wael, Belgacem, Hamdi, Rodrigues, Eduardo M. G.
Format: Article
Language:English
Subjects:
Behavior
behavioral modelling
Electric potential
Extraction procedures
Fourier transforms
I/O
IBIS
Multilayers
Noise
nonlinear dynamic circuits
Nonlinear dynamics
power supply induced jitter
Semiconductor devices
Simulation
Supplies
Transistors
Vibration
VLSI
Voltage
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Summary:This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.
ISSN:1424-8220
1424-8220
DOI:10.3390/s21186074