Mitigation of capacitor voltage unbalance and common mode voltage for 3-phase 5-Level NPC inverter using hexagonal SVPWM

• Published in: e-Prime 2024-09, Vol.9, p.100639, Article 100639
• Main Author: Palanisamy, R.
• Format: Article
• Language: English
• Subjects: Capacitor Voltage Unbalance (CVU); CMV; Neutral point clamped inverter (NPCI); Space vector pulse width modulation (SVPWM); Total Harmonic Distortion (THD)
• ISSN: 2772-6711; 2772-6711
• DOI: 10.1016/j.prime.2024.100639

•The proposed system's CMV is dropped to 12.5 V (Vdc/12 times the supplied dc source voltage).•The CVU is reduced to 0.55 percent, which is a enhanced reduction than other PWM approaches.•THD of 3-phase 5-level NPCI has been diminished to 3.12 % for voltage and 3.69 % for current.•Three-phase-five-level NPCI is developed using SVPWM with NSV scheme. Capacitor Voltage Unbalance and Common Mode Voltage (CMV) issues leads to affects the performance of the inverter, magnitude of load current increase and THD increase. So to diminish unbalance in the capacitor voltage and CMV, a hexagonal based Space Vector Pulse Width Modulation (SVPWM) is implemented for three-phase five-level Neutral Point Clamped inverter (NPCI) at high modulation index of 0.905. The performance of the inverter is improved, when the number of level of inverter increases. Simultaneously, the switching pulse creation becomes more sophisticated. SVPWM is a digital PWM control approach that maximizes the use of the dc link voltage while lowering the system's THD. And capacitor voltage (CV) imbalance and CMV are reduced by adopting the Nearest-State-Vector (NSV) technique, which selects only null, small, and large vectors and ignores medium vectors. Using Matlab Simulink and an FPGA processor, the proposes system's simulation and experimental results are established.