GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integrat...

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Bibliographic Details
Published in:IEEE journal of the Electron Devices Society 2017-05, Vol.5 (3), p.164-169
Main Authors: Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Fossum, Jerry G.
Format: Article
Language:English
Subjects:
FinFET
FinFETs
G-S/D underlap
GAAFET
Gallium arsenide
High-k dielectric materials
Ions
Logic gates
Pragmatics
Resistance
ultra-thin body
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Summary:Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.
ISSN:2168-6734
2168-6734
DOI:10.1109/JEDS.2017.2689738