Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided...

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Bibliographic Details
Published in:IEEE journal of the Electron Devices Society 2020, Vol.8, p.1390-1396
Main Authors: Lee, Jia-Wei, Chiang, Meng-Hsueh
Format: Article
Language:English
Subjects:
compact model
Electric fields
Electrodes
Heating systems
Leakage current
Leakage currents
logic in memory
Modelling
Resistance
Resistive random access memory (RRAM)
selectorless RRAM
Switches
Tunneling
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Summary:This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.
ISSN:2168-6734
2168-6734
DOI:10.1109/JEDS.2020.3008172