28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery

A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event...

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Bibliographic Details
Published in:IEEE access 2019, Vol.7, p.47955-47961
Main Authors: Yuan, Hengzhou, Guo, Yang, Chen, Jianjun, Chi, Yaqing, Chen, Xi, Liang, Bin
Format: Article
Language:English
Subjects:
Bit error rate
Clock and data recovery
Clock recovery
Clocks
CMOS
Data recovery
Error correction
Fault tolerance
Finite state machines
Frequency conversion
frequency divider
Frequency dividers
Hardening
hardening by design
Heavy ions
Ions
Performance degradation
Phase frequency detector
Phase locked loops
Single event upsets
Soft errors
Voltage-controlled oscillators
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Summary:A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event transient (SET) accumulation in different finite-state machines (FSMs). Our proposed divider also does not destroy the original structure and can, thus, greatly reduce performance degradation. Laser tests show that the threshold of the proposed divider can be significantly improved. The heavy-ion experiment shows good SET/single-event upset (SEU) tolerance during the ion strike under 83.7 MeV \cdot cm 2 /mg.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2019.2906884