Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

• Published in: Energies (Basel) 2020-05, Vol.13 (10), p.2628
• Main Authors: Elangovan, Surya, Cheng, Stone, Chang, Edward Yi
• Format: Article
• Language: English
• Subjects: Bias; cascode configuration; Cascode devices; Collapse; Degradation; Delay; device degradation; Dynamic stability; Electric vehicles; electronic trapping effects; Experiments; Failure mechanisms; Gallium; gallium nitride HEMT; Gallium nitrides; Insulators; Interfaces; Market penetration; MIS (semiconductors); off-state gate bias stress; Reliability; Room temperature; Stress; Transconductance; Transistors; Trapping; Voltage
• ISSN: 1996-1073; 1996-1073
• DOI: 10.3390/en13102628

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.