A fast and efficient data reuse scheme for HEVC Integer Motion Estimation hardware architecture

• Published in: Journal of information and telecommunication (Print) 2024-07, p.1-18
• Main Author: Duc Khai, Lam
• Format: Article
• Language: English
• Subjects: accelerator; FPGA; hardware design; High-efficiency video coding; motion estimation; real-time
• ISSN: 2475-1839; 2475-1847
• DOI: 10.1080/24751839.2024.2381310

High-Efficiency Video Coding (HEVC) is a video compression standard designed to improve video compression efficiency compared to its predecessor, Advanced Video Coding (AVC). HEVC provides approximately twice the compression efficiency compared to the AVC. In the HEVC system, the most computational complexity module is the Motion Estimation (ME). ME module helps reduce redundancy by compensating for motion during video compression. However, the computational complexity makes it a bottleneck in the design of high-resolution video encoders. This paper proposes an efficient architecture for the Integer ME (IME) module of the HEVC encoder. The proposed architecture introduces an efficient memory usage scheme to support the Full Search motion search algorithm. The full pipeline architecture includes 4096 Processing Elements (PE) and an adder tree to compute the Sum of Absolute Difference (SAD) for every Prediction Unit (PU) partition. The proposed architecture was designed and implemented on Xilinx Virtex-7 XC7VX550T FPGA. Our design achieved up to 275 FPS and approximately 10 FPS at 4 K video for the Search Regions of [Formula: see text] and [Formula: see text] pixels, respectively.