FPGA Interconnect Topologies Exploration

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. T...

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Bibliographic Details
Published in:International journal of reconfigurable computing 2009-01, Vol.2009 (2009), p.1-13
Main Authors: Mehrez, Habib, Farooq, Umer, Mrabet, Hayder, Marrakchi, Zied
Format: Article
Language:English
Subjects:
Computer Science
Critical path
Field programmable gate arrays
Logic
Studies
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Summary:This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.
ISSN:1687-7195
1687-7209
DOI:10.1155/2009/259837