An optimized two-level discrete wavelet implementation using residue number system

Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using resi...

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Bibliographic Details
Published in:EURASIP journal on advances in signal processing 2018-06, Vol.2018 (1), p.1-16, Article 41
Main Authors: Alzaq, Husam Y., Ustundag, B. Berk
Format: Article
Language:English
Subjects:
Digital integrated circuits
Digital signal processing (DSP)
Discrete Wavelet Transform
Discrete wavelet transform (DWT)
Engineering
Field programmable gate array (FPGA)
Number systems
Power consumption
Quantum Information Technology
Rams
Residue number system (RNS)
Residue number systems
Signal processing
Signal,Image and Speech Processing
Spintronics
Technology application
Wavelet transforms
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Summary:Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.
ISSN:1687-6180
1687-6172
1687-6180
DOI:10.1186/s13634-018-0559-3