Sidewall Slope Control of InP Via Holes for 3D Integration

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature...

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Bibliographic Details
Published in:Micromachines (Basel) 2021-01, Vol.12 (1), p.89
Main Authors: Lee, Jongwon, Roh, Kilsun, Lim, Sung-Kyu, Kim, Youngsu
Format: Article
Language:English
Subjects:
3D integration
Gas mixtures
Inductively coupled plasma
InP
Metals
Morphology
Plasma etching
Room temperature
Selectivity
Silicon dioxide
through substrate via (TSV)
Transistors
via hole
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Summary:This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl /Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO selectivity with RF power.
ISSN:2072-666X
2072-666X
DOI:10.3390/mi12010089