A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant imp...

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Bibliographic Details
Published in:International journal of antennas and propagation 2012-01, Vol.2012 (2012), p.1-10
Main Authors: Chang, Dau-Chyrh, Zhang, Lihong, Yang, Xiaoling, Yen, Shao-Hsiang, Yu, Wenhua
Format: Article
Language:English
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Summary:We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.
ISSN:1687-5869
1687-5877
DOI:10.1155/2012/851465