FPGA Realization of a Fractional-Order Model of Universal Memory Elements

• Published in: Fractal and fractional 2024-10, Vol.8 (10), p.605
• Main Authors: Afolabi, Opeyemi-Micheal, Adeyemi, Vincent-Ademola, Tlelo-Cuautle, Esteban, Nuñez-Perez, Jose-Cruz
• Format: Article
• Language: English
• Subjects: Behavior; Commercialization; Computer engineering; Digital integrated circuits; Electric currents; Electrical engineering; Emulators; Field programmable gate arrays; FOME; FPGA; fractional order; Hardware; hybrid systems; Impact analysis; Industrial applications; Memory devices; memory elements; Nanomaterials; Order parameters; Power management; Resource utilization; Semiconductors; Signal processing; Simulation methods; Solid state devices; Thin films; Topology; Transistors; universal memelements; Variables
• ISSN: 2504-3110; 2504-3110
• DOI: 10.3390/fractalfract8100605

This paper addresses critical gaps in the digital implementations of fractional-order memelement emulators, particularly given the challenges associated with the development of solid-state devices using nanomaterials. Despite the potentials of these devices for industrial applications, the digital implementation of fractional-order models has received limited attention. This research contributes to bridging this knowledge gap by presenting the FPGA realization of the memelements based on a universal voltage-controlled circuit topology. The digital emulators successfully exhibit the pinched hysteresis behaviors of memristors, memcapacitors, and meminductors, showing the retention of historical states of their constitutive electronic variables. Additionally, we analyze the impact of the fractional-order parameters and excitation frequencies on the behaviors of the memelements. The design methodology involves using Xilinx System Generator for DSP blocks to lay out the architectures of the emulators, with synthesis and gate-level implementation performed on the Xilinx Artix-7 AC701 Evaluation kit, where resource utilization on hardware accounts for about 1% of available hardware resources. Further hardware analysis shows successful timing validation and low power consumption across all designs, with an average on-chip power of 0.23 Watts and average worst negative slack of 0.6 ns against a 5 ns constraint. We validate these results with Matlab 2020b simulations, which aligns with the hardware models.